1. Field of the Invention
The invention relates, in general, to a method of manufacturing a NAND flash memory device and, more particularly, to a method of manufacturing a NAND flash memory device, wherein program disturbance can be improved.
2. Discussion of Related Art
A NAND flash memory has a string structure in which source select line (SSL) and drain select line (DSL) gates and 16 to 64 cell gates are arranged in series between a source line and a bit line. The source select line (SSL) and drain select line (DSL) gates are generally greater than the cell gates. The number of cell gates arranged in the first string is generally 32 due to the limit of a cell current.
The cell program of the flash memory device is performed in such a manner that a voltage of 15V to 20V is applied to a selected cell gate and a pass voltage (Vpass) of about 10V is applied to a non-selected cell gate so that carriers introduced into the bit line pass through the gate insulating layer of the selected cell gate and charge the floating gate.
In general, the NAND flash memory device employs a method of applying 0V to the bit line in order to improve the charge efficiency of a selected channel and self-boosting a non-selected channel in order to prohibit program disturbance.
If the level of integration increases and the gate design rules are complicated, however, GIDL (gate induced drain leakage) is generated at the drain of the drain select line DSL or the source select line SSL of a non-selected cell string at the time of the self-boosting operation. Accordingly, program disturbance occurs in which unwanted electrons are injected into neighboring memory cells and the cells are programmed. This results in an abrupt decrease in the reliability and yield of devices.
If the distance between the source select line SSL and the drain select line DSL and neighboring memory cells is sufficiently secured, program disturbance can be controlled up to 90 nm. It is, however, to difficult to secure a sufficient distance as the level of integration is increased. To solve the problem, a method of reducing the size of the drain select line DSL and the source select line SSL has been proposed.
If the size of the source select line SSL is reduced, however, a punch-off leakage current is caused between a boosting channel of a non-selected bit line and a common source at the time of program. This causes to lower the channel boosting level, leading to aggravated program disturbance.
Furthermore, if the size of the drain select line DSL is reduced, the threshold voltage Vt of the drain select transistor is lowered. Accordingly, the channel precharge voltage level is lowered and the boosting level is lowered, resulting in aggravated program disturbance.